With the development of semiconductor technology, semiconductor products are developed to have low power consumption and low cost, thus, a power-supply voltage of a memory is relatively low. However, to realize reading and writing of stored information, a voltage for programming and erasing, which is much higher than the power-supply voltage, is required. Therefore, charge pump systems, which are used to generate a high voltage for programming and erasing from a low power-supply voltage, are widely used in memories.
FIG. 1 schematically illustrates a structural diagram of a charge pump system in existing techniques. Referring to FIG. 1, the charge pump system includes a clock oscillating unit 11, a charge pump circuit 12, a voltage dividing unit 13, a reference voltage generating unit 14 and a voltage comparing unit 15.
An operation process of the charge pump system is described as follows. When the charge pump system is started, the clock oscillator unit 11 generates a clock signal Clk after receiving an oscillation enabling signal, the charge pump circuit 12 boosts a power-supply voltage of the charge pump system to obtain a boosting voltage VEP after receiving a charge pump enabling signal and the clock signal Clk, the voltage dividing unit 13 divides the boosting voltage VEP to obtain a division voltage VDI, the reference voltage generating unit 14 generates a reference voltage VREF, and the voltage comparing unit 15 compares the division voltage VDI with the reference voltage VREF.
Specifically, when the boosting voltage VEP is lower than a predetermined voltage (for example, a voltage for driving loads of the charge pump system to operate), the division voltage VDI output from the voltage dividing unit 13 is lower than the reference voltage VREF. Then, the voltage comparing unit 15 may output a voltage boosting enabling signal, to enable the clock oscillator unit 11 to output the clock signal Clk. The charge pump circuit 12 will obtain the boosting voltage under the control of the clock signal Clk.
When the boosting voltage VEP is higher than the predetermined voltage, the division voltage VDI output from the voltage dividing unit 13 is higher than the reference voltage VREF. The voltage comparing unit 15 may output an invalidation signal, to enable the clock oscillator unit 11 to stop oscillating. Thus, the clock oscillator unit 11 will stop providing the clock signal Clk to the charge pump circuit 12, so that the charge pump circuit 12 stops the voltage boosting process.
From above, when the boosting voltage VEP is higher than the predetermined voltage, the charge pump circuit 12 stops working, thereby reducing power consumption of the charge pump system. However, in practice, the charge pump system causes great power consumption in a start-up process.